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XLS
Accelerated high-level hardware synthesis from Google
Apache-2.0
ABOUT
Hardware IP is usually written at RTL and reimplemented as host models. XLS compiles one high-level description to synthesizable Verilog and native software so teams keep a single source for silicon and simulation.
INTEGRATION GUIDE
1. Compile a DSLX function into pipelined synthesizable Verilog
2. Run the same XLS design as host software for fast simulation
3. Formally check that generated hardware matches the software model
4. Prototype a hardware accelerator without starting from Verilog
TAGS
xlshlsverilogsystemveriloggooglehardwaresynthesiseda