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VUNIT
Unit testing framework for VHDL and SystemVerilog
MPL-2.0
ABOUT
HDL tests are often one-off simulator scripts with no discovery or reporting. VUnit compiles, simulates, and checks VHDL and SystemVerilog from Python so teams run unit tests like software CI.
INSTALL
pip install vunit-hdlINTEGRATION GUIDE
1. Write VHDL unit tests and run them from a Python VUnit runner
2. Drive GHDL, NVC, or a vendor simulator from one test suite
3. Scan a project for testbenches and report pass or fail in CI
4. Mix SystemVerilog testbenches with the same VUnit runner
TAGS
vunitvhdlsystemverilogtestingsimulationfpgaverification