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VEXRISCV
FPGA-friendly 32-bit RISC-V CPU written in SpinalHDL
MIT
ABOUT
Soft RISC-V cores on FPGA are often rigid or licensed. VexRiscv generates a 32-bit pipeline in SpinalHDL with plugins for caches, FPU, MMU, and custom instructions so teams size the core to the FPGA and still boot Linux or run bare metal.
INTEGRATION GUIDE
1. Generate a cached RISC-V core for an FPGA SoC without licensed CPU IP
2. Add custom instructions or CSRs through the VexRiscv plugin system
3. Boot Linux on a VexRiscv configuration with MMU and caches
4. Simulate the CPU with Verilator and debug via GDB and OpenOCD
TAGS
vexriscvrisc-vcpufpgaspinalhdlhdllinux