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VERYL
Modern SystemVerilog-based hardware description language
Apache-2.0
ABOUT
SystemVerilog is powerful but verbose and easy to write in ways that will not synthesize. Veryl is a modern HDL that transpiles to readable SV with tooling so teams keep SV interoperability without the boilerplate.
INSTALL
cargo install verylINTEGRATION GUIDE
1. Write synthesizable RTL in Veryl and transpile it to SystemVerilog
2. Mix Veryl modules with an existing SystemVerilog IP library
3. Format and lint HDL in VS Code, Vim, or Emacs with Veryl tooling
4. Teach digital design with a simpler syntax that still emits SV
TAGS
verylhdlsystemverilogfpgartlrusteda