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VERIBLE
SystemVerilog parser, style linter, and formatter
Apache-2.0
ABOUT
SystemVerilog is hard to parse, so every linter and formatter used to ship a fragile custom frontend. Verible provides a shared IEEE 1800 parser plus style lint and format so teams check un-preprocessed RTL without writing another SV parser.
INTEGRATION GUIDE
1. Lint SystemVerilog style across a chip repo in CI
2. Format SV sources with a shared, parser-based formatter
3. Parse un-preprocessed IEEE 1800 files for custom developer tools
4. Check language compliance against the sv-tests suite
TAGS
veriblesystemveriloglinterformatterparserrtlchipsalliance