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UHDM
Compiled SystemVerilog interchange format for open EDA tools
Apache-2.0
ABOUT
Open EDA tools each reimplement SystemVerilog parsing and disagree on elaboration. UHDM is a compiled IEEE object model with VPI so Surelog, Yosys, and simulators share one interchange format.
INSTALL
brew install uhdmINTEGRATION GUIDE
1. Read a Surelog-elaborated design into Yosys through UHDM
2. Serialize a SystemVerilog object model for a custom linter
3. Visit elaborated SV with the UHDM listener and VPI APIs
4. Share one compiled design between a simulator and a synthesis tool
TAGS
uhdmsystemverilogsurelogyosysvpihdledachipsalliance