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SYSTEMC
C++ library for system-level hardware modeling and simulation
Apache-2.0
ABOUT
SoC architecture is too late to debug once RTL is frozen. SystemC models clocks, signals, and TLM transactions in C++ so teams simulate interconnects, accelerators, and firmware before committing to Verilog.
INTEGRATION GUIDE
1. Simulate a SoC interconnect before writing RTL
2. Model an ML accelerator at transaction level with TLM
3. Co-simulate firmware against a SystemC virtual platform
4. Explore architecture tradeoffs in C++ instead of gate-level sims
TAGS
systemchardwaretlmsocsimulationc++verificationesl