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SVLINT
IEEE 1800-2017 SystemVerilog linter
MIT
ABOUT
SystemVerilog style and syntax issues often wait until a simulator or synthesis run. svlint checks IEEE 1800-2017 RTL with configurable rules so teams catch problems in the editor before a long compile.
INSTALL
cargo install svlintINTEGRATION GUIDE
1. Lint SystemVerilog RTL in CI with a project rule file
2. Catch non-synthesizable constructs before a Yosys or Vivado run
3. Pair svlint with the svls language server in an editor
4. Enforce a parse-only or style ruleset across an FPGA codebase
TAGS
svlintsystemveriloglinterhdlrustfpgaasiceda