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SV2V
SystemVerilog-to-Verilog converter for open synthesis flows
BSD-3-Clause
ABOUT
Many open synthesizers still expect Verilog, not full SystemVerilog. sv2v converts IEEE 1800 sources to IEEE 1364 Verilog so teams keep packages, interfaces, and logic types without a commercial frontend.
INTEGRATION GUIDE
1. Convert a SystemVerilog design to Verilog before a Yosys synthesis run
2. Pass through Yosys-supported SV features and convert the rest
3. Write adjacent .v files for every .sv source in a project
4. Feed converted Verilog to Icarus or another Verilog-only simulator
TAGS
sv2vsystemverilogverilogyosyssynthesishdlconversion