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SURELOG
SystemVerilog 2017 frontend and UHDM compiler
Apache-2.0
ABOUT
Open synthesis and lint tools each reimplement SystemVerilog parsing and miss testbench constructs. Surelog compiles IEEE SV 2017 to UHDM so Yosys, simulators, and linters share one frontend instead of forking their own parsers.
INSTALL
brew install surelogINTEGRATION GUIDE
1. Elaborate a SystemVerilog design into a UHDM database for Yosys
2. Lint SV with a Python visitor over the Surelog AST
3. Feed an open simulator or formal tool from a serialized UHDM model
4. Compile UVM packages once and reuse them across verification runs
TAGS
surelogsystemveriloguhdmparserelaboratoryosyshdleda