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SPINALHDL
Scala-based HDL that generates VHDL and Verilog
LGPL-3.0
ABOUT
Verilog and VHDL are verbose and weakly structured for large designs. SpinalHDL lets teams describe hardware in Scala with types, objects, and functions, then emit VHDL or Verilog so FPGA and ASIC flows stay compatible without writing the RTL by hand.
INTEGRATION GUIDE
1. Describe a digital core in Scala and emit Verilog or VHDL for synthesis
2. Reuse object-oriented hardware generators across FPGA projects
3. Generate a SoC interconnect or peripheral from typed SpinalHDL components
4. Mix SpinalHDL IP with existing Verilog testbenches and EDA tools
TAGS
spinalhdlhdlscalaverilogvhdlfpgaasic