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SILICE
HDL for pipelined algorithms on FPGA hardware
GPL-3.0
ABOUT
FPGA algorithms in Verilog mix pipeline stages by hand and stay hard to retarget. Silice describes algorithms, pipelines, and cycle logic in one language, then emits Verilog for open or vendor toolchains without a closed HLS compiler.
INTEGRATION GUIDE
1. Describe a pipelined FPGA algorithm and emit Verilog for synthesis
2. Prototype a RISC-V core or GPU-style rasterizer on a supported board
3. Combine per-cycle logic with multi-cycle algorithms in one HDL
4. Simulate and formally verify Silice designs before FPGA bring-up
TAGS
silicehdlfpgaverilogpipelinesrisc-v