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ROCKET CHIP
Chisel generator for parameterized RISC-V Rocket SoCs
BSD-3-Clause
ABOUT
Building a RISC-V SoC means wiring a core, caches, bus, and devices in RTL by hand. Rocket Chip generates a parameterized Rocket core and TileLink system in Chisel so teams simulate, FPGA-prototype, or tape out a Linux-capable chip from config.
INTEGRATION GUIDE
1. Generate a parameterized RISC-V SoC with Rocket cores and TileLink
2. Cycle-accurate Verilator simulation of a Rocket Chip configuration
3. Map a Rocket core to FPGA for software bring-up before silicon
4. Push a Rocket Chip instance through an open or commercial VLSI flow
TAGS
rocket-chiprisc-vchiselsoccpufpgachipsalliance