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OPENROAD
Open-source RTL-to-GDSII digital implementation flow
BSD-3-Clause
ABOUT
Taking RTL to a manufacturable GDSII layout usually needs a stack of licensed EDA tools. OpenROAD runs floorplan, place, clock tree, route, and timing in one open application so research and startup chip teams can implement designs without that lock-in.
INTEGRATION GUIDE
1. Run an RTL-to-GDSII flow from Verilog through place and route
2. Tune floorplan, density, and timing constraints in an open ASIC flow
3. Teach physical design with a free implementation tool instead of vendor GUI seats
4. Script chip implementation experiments without a closed EDA license
TAGS
openroadasicrtlgdsiiedaplacementroutingtiming