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OPENLANE
Automated open-source RTL-to-GDSII ASIC implementation flow
Apache-2.0
ABOUT
Tape-out quality GDSII usually needs a stack of licensed EDA tools for synthesis, place, route, DRC, and GDS. OpenLane scripts those steps around OpenROAD and open PDKs so research and shuttle teams can harden Verilog to layout without vendor lock-in.
INTEGRATION GUIDE
1. Harden Verilog RTL to GDSII for an open PDK shuttle run
2. Explore design variants with OpenROAD, Yosys, Magic, and KLayout in one flow
3. Reproduce Google MPW and chipIgnite tapeouts with a containerized ASIC flow
4. Teach digital implementation without closed-source EDA licenses
TAGS
openlaneasicrtlgdsiiedaopenroadyosystapeout