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MYHDL
Python as a hardware description and verification language
LGPL-2.1
ABOUT
Hardware teams bounce between Python testbenches and separate VHDL or Verilog models. MyHDL describes and verifies digital logic in Python, then converts to VHDL or Verilog so simulation and synthesis stay in one language.
INSTALL
pip install myhdlINTEGRATION GUIDE
1. Model a digital circuit in Python and convert it to Verilog or VHDL
2. Write Python testbenches that co-simulate with converted RTL
3. Teach hardware design with Python instead of starting in Verilog
4. Prototype FPGA logic without leaving the Python toolchain
TAGS
myhdlpythonhdlverilogvhdlfpgaverification