All Tools
L
Dev ToolsFreeOpen Source
LITEX
Python framework for building FPGA SoCs
BSD-2-Clause
ABOUT
Custom FPGA SoCs mean wiring a CPU, bus, DRAM, and peripherals in Verilog by hand. LiteX generates that infrastructure in Python so teams pick a core, add LiteX cores, and get a synthesizable SoC plus BIOS without a vendor SoC builder.
INSTALL
pip install litexINTEGRATION GUIDE
1. Generate a RISC-V FPGA SoC with DRAM, UART, and Ethernet from Python
2. Mix LiteX cores with custom Amaranth or Verilog IP on one bus
3. Boot a LiteX BIOS and Linux-capable system on a supported board
4. Prototype an accelerator SoC without writing interconnect RTL
TAGS
litexfpgasocpythonrisc-vhdlmigen