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LIBRELANE
Open-source ASIC flow infrastructure, successor to OpenLane
Apache-2.0
ABOUT
OpenLane was a scripted RTL-to-GDSII wrapper that is hard to extend. LibreLane rebuilds that flow as a Python infrastructure library with hermetic steps and plugins so teams customize ASIC implementation without a closed EDA stack.
INSTALL
pip install librelaneINTEGRATION GUIDE
1. Harden Verilog RTL to GDSII on an open PDK such as sky130
2. Write a Python plugin that inserts a custom ECO into the ASIC flow
3. Replay a hermetic step snapshot after changing one flow config
4. Teach digital implementation with Classic and Chip reference flows
TAGS
librelaneopenlaneasicrtlgdsiiedapdktapeout