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HARDCAML
OCaml library for typed hardware design and RTL generation
MIT
ABOUT
Verilog and VHDL are weakly typed and hard to parameterize. Hardcaml lets teams describe circuits in OCaml, simulate them, and emit hierarchical Verilog or VHDL without a closed HLS toolchain.
INSTALL
opam install hardcamlINTEGRATION GUIDE
1. Describe a circuit in OCaml and emit hierarchical Verilog or VHDL
2. Simulate a design in OCaml and print ASCII waveforms with waveterm
3. Parameterize hardware generators with OCaml functors and functions
4. Convert a Hardcaml design to a Verilator model for faster simulation
TAGS
hardcamlocamlhdlrtlverilogvhdlfpgasimulation