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CVA6
Configurable 6-stage RISC-V core that can boot Linux
Solderpad-0.51
ABOUT
Linux-capable RISC-V cores are often closed or split across incompatible RTL trees. CVA6 is a configurable 6-stage in-order core with MMU, TLBs, and privilege modes so teams boot Unix-like OS images on FPGA or ASIC from one open design.
INTEGRATION GUIDE
1. Boot Linux on a 64-bit CVA6 application-class configuration
2. Configure a smaller CVA6 core for an embedded RISC-V SoC
3. Simulate CVA6 with Verilator and the CORE-V APU testbench
4. Evaluate microarchitecture changes with the CVA6 performance model
TAGS
cva6risc-vcpulinuxopenhwasicfpga