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COCOTB
Python testbenches for HDL chip verification
BSD-3-Clause
ABOUT
Chip verification usually means SystemVerilog testbenches and licensed simulators. cocotb lets Python coroutines drive clocks, poke signals, and check RTL through existing simulators so hardware teams reuse Python tests instead of a second HDL verification language.
INSTALL
pip install cocotbINTEGRATION GUIDE
1. Write a Python testbench that drives a Verilog or VHDL DUT
2. Run cocotb regressions with Verilator, Icarus Verilog, or GHDL
3. Reuse Python models and numpy checks against cycle-accurate RTL
4. Teach hardware verification without a SystemVerilog UVM stack
TAGS
cocotbhdlpythonverificationrtlverilogvhdl