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CLASH
Haskell-to-VHDL/Verilog compiler for typed hardware design
BSD-2-Clause
ABOUT
RTL in Verilog or VHDL is weakly typed and hard to parameterize. Clash lets teams describe circuits in Haskell with type-safe clocks and a REPL, then emit VHDL, Verilog, or SystemVerilog for synthesis without a closed HLS toolchain.
INTEGRATION GUIDE
1. Describe a synchronous circuit in Haskell and emit Verilog or VHDL
2. Load a design in the Clash REPL and test components without a testbench
3. Use type-safe clock domains when crossing clock boundaries
4. Parameterize hardware generators with Haskell higher-order functions
TAGS
clashhdlhaskellverilogvhdlfpgaasic