All Tools
A
Dev ToolsFreeOpen Source
AMARANTH
Python HDL and toolchain for digital hardware
BSD-2-Clause
ABOUT
Verilog is verbose and sits outside the Python stack most hardware teams already use for tests and tooling. Amaranth lets you describe synchronous digital logic in Python, simulate it, and emit Verilog for FPGA synthesis without a separate HDL language.
INSTALL
pip install amaranthINTEGRATION GUIDE
1. Describe an FPGA core in Python and emit Verilog for Yosys or vendor tools
2. Simulate synchronous logic with Amaranth's built-in Python simulator
3. Generate parameterized hardware from Python instead of Verilog generate blocks
4. Teach digital design with Python before introducing Verilog syntax
TAGS
amaranthhdlpythonfpgaverilogrtl