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ABC
Sequential logic synthesis and formal verification library
BSD
ABOUT
Gate-level optimization and sequential verification need a synthesis kernel most teams cannot license. ABC rewrites AIGs, maps logic, and proves properties so Yosys and open ASIC flows optimize netlists without a closed kernel.
INTEGRATION GUIDE
1. Rewrite an AIG netlist to cut area or delay before technology mapping
2. Embed libabc in Yosys for sequential optimization passes
3. Prove a combinational miter with ABC's SAT and BDD engines
4. Teach logic synthesis with a free Berkeley toolkit
TAGS
abclogic-synthesisformal-verificationyosysasicfpgaedaaig